Recently, the trends of fabricating integrated circuit (IC) chips are toward a three-dimensional stacking technology. In other words, the three-dimensional stacking technology is very potential. By means of the three-dimensional stacking technology, chips with different functions and on different substrates may be individually produced by proper fabricating processes and then combined together in a three-dimensional stacking manner. As such, the metallic wire length is shortened and the wire connection resistance is reduced to comply with the miniaturizing and power-saving requirements.
FIGS. 1A, 1B and 1C are schematic views illustrating a process of stacking an integrated circuit (IC) wafer on a carrier having the same shape according to the prior art. The integrated circuit wafer is attachable on the carrier according to a three-dimensional stacking technology. The common carrier is for example a glass substrate or a semiconductor substrate. As shown in FIG. 1A, an adhesive layer 12 is formed on a carrier by spin-coating an adhesive. Due to the cohesion of the adhesive, a thicker hump 120 is formed at the edge of the carrier 11. For enhancing the efficacy of bonding the carrier 11 and the wafer 10, the hump 120 at the edge of the carrier 11 is removed by solvent. As such, the adhesive layer 12 on the carrier 11 has better uniformity (see FIG. 1B). After the hump 120 at the edge of the carrier 11 is removed, a gap 13 is formed between the carrier 11 and the wafer 10 (see FIG. 1C). In this situation, the wafer 10 fails to be properly supported, and thus the edge of the wafer 10 is readily broken. The broken part of the wafer 10 results in contamination. The problem becomes more serious as the wafer 10 becomes thinner and thinner.
Therefore, there is a need of providing improved stacking method and carrier in order to obviate the drawbacks encountered from the prior art.